Computer memories can be categorized into two main types depending on their access characteristics. One type is random access memory (RAM) in which information can be written in and read out of the memory at any location, in any desired sequence with a similar access time for each location.
A second type of computer memory is a read only memory (ROM) in which information can be read out much like a RAM but cannot be written in as freely.
A random access memory typically consists of a plurality of memory cells, an address decoder, read/write control circuitry and a memory output register. There are many details and variations in the connection of the elements and in the structure of each element between various types of memories. A major point of variation between random access memories is the structure of the memory cells used in the memory.
In particular, there are two types of RAM memories commonly in use. In a so-called static RAM memory each cell consists of a flip/flop circuit. Thus, as long as power is supplied to the memory cells the information stored in the cells will be maintained. A flip/flop circuit typically consists of two transistors or other semiconductor devices and has two stable states.
The other type of RAM memory is called a dynamic memory. Each memory cell of the dynamic RAM memory stores information by storing electric charge in a very small capacitance, which is usually called a storage capacitance. Information in the form of "0"s and "1"s is represented by either an electric charge or no charge on the storage capacitance of a particular memory cell. A single transistor is usually used to control the charging of the storage capacitance.
Since the electric charge stored on the storage capacitance gradually leaks away information must periodically be rewritten into the cell before the charge completely leaks out. This periodic rewriting of the information is called "refreshing" the memory. The refreshing frequency depends on the amount of leakage in the control transistor--in a typical dynamic memory refreshing is required every two milliseconds or less.
Although the refreshing operation requires additional circuitry to coordinate the procedure, the dynamic RAM is often used due to certain advantages over the static RAM. For example, because only one control transistor is used in the dynamic RAM instead of two flip/flop transistors in the static RAM, the dynamic RAM occupies a much smaller area than the static RAM. In addition, the dynamic RAM is usually faster and consumes less power. Thus, dynamic RAMS are particularly attractive in mini and micro computers where space and power consumption are at a premium.
In a dynamic RAM, both a memory access (a read or a write to a memory cell) and a refresh operation are performed under control of a combination of signals called a row address strobe (RAS) signals and column address strobe (CAS) signals. In a memory access operation, the RAS and CAS signals are used to select the particular memory cell which is to be accessed. Some dynamic memories require manipulation of both the RAS and the CAS signals to perform a refresh cycle. Other memories can be refreshed by activating the RAS signal.
During a conventional refresh operation, information is read out of a plurality of cells and then rewritten back into the cells where it will remain for up to two milliseconds--the maximum refresh time limit. Conventional refresh circuitry is usually arranged so that a refresh cycle occurs after each memory access. Normally, a whole row of memory cells is refreshed at once. Thus, an access to any cell in a particular row causes the entire row to be refreshed.
Conventional refresh circuitry works well when a sufficient number of memory accesses to refresh the entire memory can be guaranteed within the maximum refresh time limit. In a computer system which has a single block of memory and one memory controller, a sufficient number of memory accesses usually occurs within the required time limit.
However, when a large memory is partitioned into two or more blocks, each independently accessable, then it is possible for all memory accesses occurring within the refresh time limit to occur in one block of the memory. Thus, the maximum refresh time limit for the unaccessed block may be exceeded causing information loss.
One prior art solution to avoid this latter problem is to periodically trigger a refresh cycle by means of a continuously running timer which triggers a DMA (direct memory access) cycle to force a memory refresh cycle. This arrangement insures against loss of data but wastes power and slows down the operation of the memory because unnecessary refresh cycles may be performed both during a normal memory access and immediately afterwards as prompted by the timer.
Accordingly, it is an object of the present invention to provide a memory refresh circuit which refreshes the memory when a memory access is performed.
It is another object of the present invention to provide a memory refresh circuit which can operate in a system in which the memory is partitioned into blocks.
It is a further object of the present invention to provide a memory refresh circuit which forces a refresh of the memory prior to the expiration of the maximum refresh time limit without requiring periodic memory refresh cycles.
It is still another object of the present invention to provide a memory refresh circuit which can prevent the maximum refresh memory time from being exceeded even though no memory accesses are attempted within the time period.